1. Field
Example embodiments relate to logic semiconductor devices. More particularly, example embodiments relate to logic semiconductor devices including multi-leveled wirings.
2. Description of the Related Art
In a logic semiconductor device including a standard cell, a logic transistor including a gate pattern may be formed on a semiconductor substrate, and wirings may be arranged over the logic transistor. As a critical dimension of the gate pattern decreases to a nano-scale, a width and a pitch of the wiring may be also reduced.
As a degree of integration of the logic semiconductor device increases, a process margin for designing the wirings may be reduced, and the wirings having a dimension less than a target value may not be easily formed due to a resolution limit of a patterning process.